The present invention relates to a construction to be used for mounting electronic parts, such as semiconductor devices or the like, and to a method for manufacturing the same. The term "construction" as used herein means not only a container or a package having a stem and a wall member for airtightly sealing electronic parts therein, but also a stem for supporting electronic parts of the type not specifically necessitating a wall member.
Generally, as one such type of electronic part mounting construction, a package or a container for a super high frequency semiconductor device has been known. In such a package, it is common practice that metallized layers electrically connected to respective electrodes of a semiconductor element are deposited on the package and external connection leads are attached to the respective metallized layers by means of soldering material. In such a package, it is necessary to minimize the parasitic inductance and parasitic capacitance caused by the metallized layers, the external connection leads and the like.
Heretofore, in order to reduce the parasitic inductance and the parasitic capacitance, a package for a semiconductor device has been proposed in which a lid member attached on the top of a wall member for airtightly sealing a semiconductor device therein is formed of a metal. This lid member and the semiconductor device on a stem of the package are electrically connected through a metallized layer formed on the inside surface of a wall member (See the specification of Japanese Patent Application No. 55-78001, the disclosure of which is incorporated herein by reference). In addition, the above-referenced specification also discloses a method for forming a metallized layer of a precise width on an inside surface of a wall member. According to the proposed method, the precisely controlled metallized layer is formed by the steps of forming a groove on the inside surface of the wall member and forming a metallized layer only in this groove.
According to the above-described proposal, it is clearly possible to reduce the parasitic capacitance and inductance. However, in the case where the metallized layer on a stem mounting a semiconductor device continuously extends to the metallized layer deposited on the inside surface of the wall member, a soldering material (for example, Au-Si) for mounting the semiconductor device is apt to flow along the metallized layer on the stem and also to climb up to the top portion of the wall member along the metallized layer on the inside surface. Since the types of solder used in mounting the semiconductor and in sealing the lid member are usually different, the lid member sealing solder may be contaminated by the solder which climbs up the metallized layer, thus resulting in a sealing failure between the lid member and the wall member. Furthermore, when the lid member is soldered to the top portion of the wall member by a soldering material such as Au-Sn, this soldering material is apt to flow out onto the metallized layer on the substrate along the metallized layer on the inside surface of the wall member, resulting in a cut-off of the metallic wirings bonded between the semiconductor element and the metallized layer on the stem.
The above-mentioned phenomenon that the soldering material climbs up along the metallized layer or flows down along the metallized layer has also been observed in the case where a metallized layer is formed on the outer peripheral surface of the stem and soldered to an external connection lead.